216NG62A HESG441634R1K HESG216876 | ABB| interrupt status register

Description

216NG62A HESG441634R1K HESG216876 | ABB| interrupt status register

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After detecting a high interrupt level, the 216NG62A HESG441634R1K HESG216876 writes a PIO write operation to bit [31] of the control status register 04H in the BAR space of PCIe, turning off the receive interrupt function. At this time, the interrupt enable signal line int_dis_o is pulled high, as shown in position “4” in the above figure. During the high level period, the CPU no longer responds to interrupt requests from the FPGA board, which is very important here. Afterwards, the CPU reads the interrupt status register of the FPGA in the form of PIO reading.
5) The 216NG62A HESG441634R1K HESG216876sends the value of the interrupt status register to the CPU in the form of a PIO read completion packet, informing the CPU of the specific type of interrupt and configuring the “clear interrupt” timing. As shown at “5” in the above figure.

6) After the CPU driver records the interrupt source, reset the corresponding interrupt flag bit, as shown in “6” in the above figure. (This can also be done by FPGA itself)

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