CP461-50 | YOKOGAWA | Buffer register module

Description

CP461-50 | YOKOGAWA | Buffer register module

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The conversion process of CP461-50 approximation method is: the successive approximation registers are cleared to zero during initialization; At the beginning of the conversion, the highest position of the successive approximation register 1 is sent to the D/A converter, and the analog generated after the conversion of D/A is sent to the comparator, called Vo, and compared with the analog Vi to be converted into the comparator. If Vo<Vi, the bit 1 is retained, otherwise it is cleared. Then the secondary high of the successive approximation register is 1, the new digit in the register is sent to the D/A converter, and the output Vo is compared with Vi, if Vo<Vi, the bit 1 is retained, otherwise it is cleared. This process is repeated until the lowest register is approached. After the conversion, the digital quantity in the successive approximation register is sent to the buffer register to obtain the digital output. The operation process of successive approximation is carried out under the control of a control circuit.

CP461-50 A/D converter with double integration method consists of electronic switch, integrator, comparator and control logic. As shown in Figure 4.22.
The basic principle is to convert the input voltage into a time interval proportional to its average value, and then convert this time interval into a digital quantity, which is an indirect conversion.

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